![]() Selectively connected to two cell inputs and with a gate Gate (44') provided therein with a pair of gate inputs Tables (45', 47') receiving signals from a common set ofĬell inputs, each logic cell (11) also having an AND logic (a 0, a 1, a 2) and an output, the address inputs of both look-up Look-up table (45', 47') having a set of address inputs Including first and second look-up tables (45', 47'), each Terminals (A, B) of the circuit, each logic cell (11) Interconnectable to each other and to input and output lookup tablesĪ field programmable gate array (FPGA) is disclosed,Ĭomprising a plurality of programmable logic cells (11) H03K19/17728- Reconfigurable logic blocks, e.g.H03K19/17724- Structural details of logic blocks.H03K19/1737- Controllable logic circuits using multiplexers.H03K19/1735- Controllable logic circuits by wiring, e.g.H03K19/1733- Controllable logic circuits.H03K19/17736- Structural details of routing resources.having at least two inputs acting on one output Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form having at least two inputs acting on one output Inverting circuits using specified components using elementary logic circuits as components having at least two inputs acting on one output Inverting circuits using specified components having at least two inputs acting on one output Inverting circuits G06F13/00- Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units.G06- COMPUTING CALCULATING OR COUNTING.Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.) Filing date Publication date Application filed by Atmel Corp filed Critical Atmel Corp Publication of EP1150431A1 publication Critical patent/EP1150431A1/en Application granted granted Critical Publication of EP1150431B1 publication Critical patent/EP1150431B1/en Anticipated expiration legal-status Critical Status Expired - Lifetime legal-status Critical Current Links Original Assignee Atmel Corp Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.) Luking Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.) Granted Application number EP01107759A Other languages German ( de) ![]() Google Patents FPGA with look-up tablesĭownload PDF Info Publication number EP1150431A1 EP1150431A1 EP01107759A EP01107759A EP1150431A1 EP 1150431 A1 EP1150431 A1 EP 1150431A1 EP 01107759 A EP01107759 A EP 01107759A EP 01107759 A EP01107759 A EP 01107759A EP 1150431 A1 EP1150431 A1 EP 1150431A1 Authority EP European Patent Office Prior art keywords cell logic output cells input Prior art date Legal status (The legal status is an assumption and is not a legal conclusion. Google Patents EP1150431A1 - FPGA with look-up tables
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